Silicon Design Engineer at Advanced Micro Devices, Inc

, , China -

Full Time

Start Date

Immediate

Expiry Date

21 Apr, 26

Salary

0.0

Posted On

21 Jan, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Silicon Design, Control Fabric, Network-On-Chip, Chiplet Interconnect, System Management, Power Management, Thermal Management, Clocking, SystemVerilog, UVM, Formal Verification, Testbench Development, Verification IP, Subsystem Verification, SOC Verification, Communication Skills

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Control Fabric (CF) IP is the backbone of AMD SOCs. We design and deliver cutting-edge technologies of network-on-chip (NoC), chiplet interconnect, remote system management unit, advanced power & thermal management, clocking, etc. The China CF IP team is the central part of global CF team. THE PERSON: AMD Values: Innovate - Collaborate – Execute. If you’re: self-motivated, passionate to push the boundary and explore new territory, believer of sharing and mutual influence, you’re exactly who we look for. Always looking for understanding IP features at system level with self-motivation to collect all related knowledge Develop comprehensive block level verification testplan for DUT, consideration for features can be covered by IP/Subsystem/SOC level verification Develop testbench and testcases with SystemVerilog/UVM/Formal verification methodologies Develop verification IP which can be reused at different levels of verification Support Subsystem and SOC level verification, and responsible for IP’s enablement in SOC PREFERRED EXPERIENCE: Excellent knowledge of design verification methodology, such as System Verilog/UVM/Formal and AI coding tools Solid experiences with simulation model creation, testbench build and driving IP DV signoff Experience of driving complex IP verification task is a plus Experience of coordinating IP/SOC or cross-IP problem solving is a plus Experience of tool/process development is a plus Experience of UPF based power-aware simulation is a plus Good communication skills and fluent English at work is necessary ACADEMIC CREDENTIALS: Master degree in EE/CS or other related domain At least 5 years of related work experience LOCATION: Shanghai, China #LI-EH1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves designing and delivering technologies related to Control Fabric IP, including network-on-chip and chiplet interconnect. The engineer will develop verification test plans, testbenches, and support subsystem and SOC level verification.