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Silicon Integration Design Engineer at LATTICE SEMICONDUCTOR CORPORATION

, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

28 Jan, 26

Salary

0.0

Posted On

30 Oct, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Hardware Integration, RTL Design, Schematic Design, Power Estimation, Size Estimation, Address Maps Generation, Pin Migration, Design Checks, Timing Analysis, FPGA Timing Model, Power Model Knowledge, Chip Bring-Up, Validation, Characterization, Collaboration, Scripting

Industry

Semiconductor Manufacturing

Description

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Detailed Description Hardware Integration Design Engineer is responsible for implementation of either sections or full chip, by understanding requirement of individual IPs, how they work together at system level and then SOC them all together. Work includes collaboration with architecture, verification and software teams. Responsibilities include scripting, rtl or schematic design, power and size estimates, generation of the address maps, working with packaging on pin migration, design checks and timing analysis. FPGA timing model and power model know-how and knowledge will be added advantage. Help with chip bring-up, validation, and characterization.

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Responsibilities

The Hardware Integration Design Engineer is responsible for implementing sections or full chips by understanding the requirements of individual IPs and how they work together at the system level. This role involves collaboration with architecture, verification, and software teams.