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Silicon Validation Engineer at Apple

, California, United States -

Full Time

Start Date

Immediate

Expiry Date

05 Aug, 26

Salary

0.0

Posted On

07 May, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Silicon Validation, SerDes, Analog Mixed Signal, High-speed Oscilloscopes, BERT, Python, Signal Integrity, USB, PCIe, DisplayPort, CTLE, DFE, FFE, CDR, PLL, Data Mining

Industry

Computers and Electronics Manufacturing

Description

In this highly visible role, you will perform lab characterization and validation of various analog & mixed signal embedded circuits; and collaborate with multi-functional teams to launch the world's most premiere mobile SoC’s. At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Silicon Validation Engineer! As a member of our dynamic group, you will have the rare and great opportunity to work on upcoming products that will delight and encourage millions of Apple’s customers every day! DESCRIPTION You will be part of a small team responsible for: • Leading efforts to bring up, validate, and characterize high-speed SerDes blocks. • Possessing hands-on experience with various high-speed SerDes architectures, including NRZ and PAM, as well as associated protocols. • Demonstrating in-depth knowledge of crucial SerDes blocks such as CTLE, DFE, FFE, CDR, and PLLs, along with their characterization and debugging processes. • Being proficient in using test and measurement equipment like high-speed oscilloscopes and BERTs. • Understanding SerDes adaptation techniques. • Experience analyzing SerDes signal integrity. • Experience with high-speed protocols such as USB, PCIe, DP, etc. • Exhibiting strong debugging and problem-solving skills, with data investigation and mining expertise. • Developing robust test methodologies to evaluate performance and calculate high-speed serial interfaces (SerDes) operating margins across PVT variations. • Supporting ATE and Product Engineering. MINIMUM QUALIFICATIONS Bachelors degree required. PREFERRED QUALIFICATIONS MSEE and relevant experience, preferred. Hands on SerDes Lab experience. Python programming experience.

Responsibilities

Lead the bring-up, validation, and characterization of high-speed SerDes blocks for mobile SoCs. Develop robust test methodologies to evaluate performance and operating margins across PVT variations.