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SMTS Design Engineer, NVEG at Micron Technology

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

23 Jan, 26

Salary

0.0

Posted On

25 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

IO Design, CMOS Technology, Signal Integrity, Power Delivery Network Design, Physical Design, High-Speed Interfaces, SerDes, Chip Architecture, EDA Tools, Python, Matlab, Mentoring, Documentation, Training, Performance Optimization, Post Silicon Activity

Industry

Semiconductor Manufacturing

Description

Design key IO design building blocks (e.g. input receiver, equalizer, SerDes, Clock distribution circuits) to meet specifications and validate functionality and performance Model parasitics and optimize signal quality in close collaboration with layout teams Optimize circuit design based on a comprehensive understanding of CMOS technology and reliability Document and review final results with experts and stakeholders Maintain technical expertise, stay informed on industry trends, and provide training to the product validation team on design architecture and features Set individual objectives according to the team's growth and milestones, manage performance reviews, and help shape strategic decisions BS in Electrical Engineering, MS or PHD preferred 10+ years of relevant experience in the semiconductor industry Deep knowledge and understanding of high-speed IO circuits performance, power and area optimization, chip architecture/floorplan Demonstrated experience in leading and mentoring others to impact organizational effectiveness and knowledge-sharing Ability to convey complex technical concepts in verbal and written form Familiarity with full-custom EDA tools (e.g. cadence, hspice, XA, verilog), with reasonable skills in Python and Matlab for design flow automation Ability to work effectively both as a collaborator and individual contributor Knowledge and understanding of SerDes, wave pipeline circuits Experience with signal/power integrity, power delivery network design, physical design Experience with post silicon activity such as providing training on product validation and implementing design fixes under constraints Experience with CMOS BSIM model and creating CMOS targets for IO roadmap Demonstrated experience with high-speed interfaces for NAND as well as DRAM (e.g. LPDDR5/LPDDR6) and other industry standard interfaces.

Responsibilities

Design key IO building blocks and validate their functionality and performance. Collaborate with layout teams to optimize circuit design and document results with stakeholders.