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SMTS Design Engineer, Pathfinding at Micron Technology
San Jose, California, United States -
Full Time

Start Date

Immediate

Expiry Date

19 Feb, 26

Salary

0.0

Posted On

21 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Circuit Modeling, Sensitivity Analyses, Validation Development, On-Silicon Test Chips, Tape-Out Revisions, Layout Coordination, Verification Processes, Mix-Signal Design, Digital IC Design, Analog IC Design, Regulator Design, Charge Pump Design, Oscillator Design, SPICE Modeling, Verilog Simulation, CADENCE Proficiency

Industry

Semiconductor Manufacturing

Description
Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits Performing circuit modeling, sensitivity analyses, and assisting in developing validation through widely recognized simulation software and tools Designing on-silicon test chips and leading required tape-out revisions Coordinating and collaborating with the layout team, including floor-planning, placement, and routing Performing verification processes with modeling and simulation using industry-standard simulators Demonstrated experience in mix-signal, digital, or analog IC design and development for volatile or nonvolatile memory technology. Proven experience in IC design with exposure to Regulator, Charge Pump, Oscillator, Current reference, Bandgap, and Comparator design experience is required. Exposure to modeling and simulation of ICs using SPICE and Verilog. 7+ years of demonstrated ability communicating with technical and non-technical team members across a large organization. BSEE or MSEE in Electrical Engineering with a minimum of 10 years of relevant Semiconductor Manufacturing experience MSEE + 10 years' post graduate mix-signal or analog IC design experience 10+ years of exposure to circuit debugging in collaboration with other engineering teams. Proficiency with UNIX and CADENCE design environment (Simulation, Schematic entry, SPF extraction).
Responsibilities
Contribute to the development of new product opportunities by assisting with the design, layout, and optimization of circuits. Collaborate with the layout team and perform verification processes using industry-standard simulators.