SMTS Silicon Design Engineer at Advanced Micro Devices, Inc

, , China -

Full Time

Start Date

Immediate

Expiry Date

23 Jun, 26

Salary

0.0

Posted On

25 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

UPF, Low-Power Architecture, RTL, Synthesis, Place And Route, STA, Verification, EDA Tools, Tcl, Python, Perl, Constraint Management, CDC/RDC, Power Integrity, Analytical Modeling, Silicon Correlation

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The goal of AMD’s Unified Power Flow Methodology (UPFM) is to establish and scale best practices for power intent definition and power-aware design across RTL, implementation, verification, and sign-off. UPFM drives consistent use of industry-standard formats (e.g., UPF) and enables automation so design teams can reliably achieve aggressive PPA (performance, power, area) targets while meeting low-power architecture requirements (isolation, level shifting, retention, power gating, DVFS). The UPFM team partners closely with front‑end, physical design, verification, and sign‑off teams to integrate power intent seamlessly into next‑generation GPUs, CPUs, and APUs using leading EDA tools and flows (e.g., Synopsys, Cadence, Siemens). JOB PURPOSE: Build, deploy, and support a world‑class, power‑aware design flow (UPF‑based) in a fast‑paced production environment—enabling robust low‑power architectures, first‑time-right integration, and predictable sign‑off across multiple programs and nodes. KEY RESPONSIBILITIES: - Develop and maintain UPF/low‑power methodology across RTL, synthesis, P&R, STA, and verification. - Own flow features for power intent generation, validation, and ingestion (UPF authoring, linting, merges, hierarchy management, ECOs). - Evaluate, qualify, and tune power‑aware capabilities in EDA tools (e.g., synthesis, implementation, CDC/RDC, PA‑simulation, formal LP checks, EM/IR/thermal). - Support place-and-route flows for power features: isolation/retention insertion, level shifters, power switch strategies, power domain floorplanning, power grid integration. - Build automation for consistency and scalability (templates, generators, checkers, dashboards; CI integration). - Deploy flows to design teams, drive training, documentation, and best practices; troubleshoot complex issues across tool/flow/design boundaries. - Partner with architects and design leads to capture power requirements (domains, states, transitions) and translate them into actionable UPF/constraints. - Ensure sign‑off closure for low‑power: UPF vs RTL/Netlist consistency, PA‑CDC/RDC, PA‑STA, LVS/DRC implications, EM/IR with multi‑domain scenarios. - Lead cross‑team debug for power‑aware failures (X‑propagation, state retention, clamp behavior, wake/sleep sequences, corner interactions). - Mentor junior engineers to scale UPFM capabilities and improve overall team productivity. SKILLS AND EXPERIENCE REQUIREMENTS: - Bachelor’s in Electrical/Computer Engineering and 12+ years low‑power/UPF/CAD experience, or Master’s with 10+ years experience. - Strong understanding of digital design and low‑power architecture: power domains/states, isolation/retention, level shifters, power gating, DVFS, multi‑rail implications. - Expert‑level UPF (IEEE 1801) authoring and integration across RTL → synthesis → P&R → verification → sign‑off. - Hands‑on with power‑aware EDA tools (representative examples): - Front‑end/Verification: Synopsys VCS + VC LP/Verdi; Cadence Xcelium/Conformal LP; Siemens Questa PA. - Synthesis/Implementation: Synopsys Design Compiler/Fusion/ICC2; Cadence Genus/Innovus. - Timing/Sign‑off: Synopsys PrimeTime/PrimePower; Cadence Tempus; static LP checkers and PA‑CDC/RDC tools. - Power Integrity: Ansys RedHawk‑SC; Cadence Voltus (EM/IR with multi‑domain analysis). - Excellent UNIX and scripting skills (Tcl mandatory; Python and/or Perl strongly preferred); experience building flow automation and CI pipelines. - Proven experience with constraint management for multi‑domain designs (clock/power intent coherence, PA‑STA). - Familiarity with CDC/RDC methodologies under power‑aware conditions (domain on/off interactions, clamp strategies). - Experience with version control (Perforce, Git) and collaborative tooling; strong documentation and training skills. - Outstanding communication, analytical debugging, and cross‑functional collaboration; highly motivated, self‑starter. NICE‑TO‑HAVE: - Experience with multi‑chip/3D IC power intent integration (chiplet, package‑aware flows). - Knowledge of power‑aware DFT/scan strategies (retention across test, power domains in ATPG). - Exposure to power telemetry/monitoring IP and firmware interactions (state orchestration). - Familiarity with power management controllers and sequencing validation (UPF states/transitions). Role Summary AMD is seeking a highly motivated engineer to drive the next generation of Unified Power-Frequency Modeling (UPFM) used across our CPU, GPU, and APU product roadmap. The ideal candidate will be passionate about bridging pre-silicon architecture modeling, post-silicon measurement, and system-level power optimization, helping AMD deliver industry-leading performance-per-watt in modern compute platforms. This role provides a unique opportunity to operate across the full silicon lifecycle—developing analytical models, integrating silicon calibration data, and enabling productization of advanced adaptive power features such as AVFS, hierarchical binning, and chiplet-level optimization. You will be a core contributor to UPFM evolution, ensuring that predictive modeling, silicon telemetry, and field data are tightly coupled in a continuously-learning modeling pipeline. Key Responsibilities Expand UPFM to incorporate emerging IPs, new technology nodes, aging models, and hierarchical SoC/power-management structures. Build parameterized analytical models capturing: Dynamic and static power, Voltage–frequency scaling, Critical-path delay and FO2-based timing, Workload-dependent switching behavior, Process variation effects (leakage, Vmin, RC, mobility). Integrate silicon data into model calibration loops; refine UPFM coefficients across product generations. Develop modeling infrastructure to support early-stage architecture planning and power budgeting. Also enable the evaluation of ROI of new power features and power-delivery innovations. Work closely with architecture, design, firmware, and production teams to ensure modeling accuracy and feature success. Support product engineers in chiplet binning, AVFS tuning, yield/power analysis, and field-return analysis. Collaborate with system teams to extend UPFM for chiplet-based systems and datacenter power constraints. Develop and maintain Python/Ruby-based modeling pipelines, data-processing infrastructure, and visualization dashboards. Automate ingestion of silicon data into UPFM to support continuous model evolution. Build scripts for sensitivity analysis, Monte Carlo modeling, regression, and parametric sweep automation. Preferred Experience Candidates with expertise in one or more of the following are strongly encouraged to apply: Power & Performance Modeling Experience modeling power for digital/analog IPs (CPUs, GPUs, accelerators). Familiarity with switching power, leakage mechanisms, IR drop, and timing/power interactions. Knowledge of V/F behavior, clocking, AVFS, voltage guardbands, and power-management architectures. Silicon Correlation & Variation Modeling Understanding of silicon variability (process variation, Vmin, FO2 timing spread, aging). Familiarity with statistical modeling, Monte Carlo analysis, or UPFM-like frameworks. Experience analyzing ring oscillator data, telemetry, or embedded monitors. Design, Firmware & Debug Knowledge Working knowledge of digital logic design, RTL fundamentals, and physical design constraints. Understanding of clock gating, power gating, voltage domains, and on-die regulation. Exposure to design-for-debug, PSS, or validation toolchains. Programming & Data Analysis Strong experience with Python (NumPy/Pandas/Scipy), Excel modeling, and scripting. Database experience (SQL, Parquet, analytics pipelines) is a plus. Ability to build reproducible modeling environments and automated analysis tools. Ideal Candidate Profile The ideal candidate is: Strong in mathematical modeling, silicon physics, and systems thinking. Excited to work hands-on with both models and real silicon data. Able to operate across architecture, design, and product disciplines. Passionate about building frameworks that guide billion-dollar product decisions. Comfortable owning end-to-end solutions—from analysis → modeling → calibration → productization. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves building, deploying, and supporting a world-class, UPF-based, power-aware design flow to enable robust low-power architectures across multiple programs and nodes. Key tasks include developing and maintaining UPF methodology, owning flow features for power intent generation, evaluating EDA tool capabilities, and ensuring sign-off closure for low-power requirements.