SMTS Silicon Design Engineer at Advanced Micro Devices, Inc

Bangalore, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

10 Sep, 26

Salary

0.0

Posted On

12 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DFx Design, SCAN, ATPG, MBIST, BSCAN, Verilog, System Verilog, Perl, Python, TCL, Tessent, Design Compiler, Spyglass, CDC, Lint, Static Timing Analysis

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a motivated DFx engineer to join our S3 SOC DFX team. In this role, you will contribute to the next generation of AMD’s silicon innovation while developing your expertise in DFx methodologies and advanced design practices. You will be part of a forward-thinking engineering organization that values learning, encourages fresh ideas, and empowers emerging talent to grow into impactful contributors who help shape the future of semiconductor technology. KEY RESPONSIBILITIES: · The successful candidate will own/lead the DFX Design architecture and implement cutting edge DFX features including SCAN, ATPG, MBIST, BSCAN, etc. · Work closely with the DFX Architecture and the various IP Design teams to align on the DFX requirements and successfully implement the DFX design · Design and develop correct by construction DFX design and support DFX verification · Work closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects. · Work with the Synthesis and PD team to ensure correct DFT implementation and timing closure. · Provide post silicon support to ensure successful bring up. PREFERRED EXPERIENCE: · Experience and understanding of ASIC DFX, synthesis, simulation and verification flow and experience of working in DFX architecture of complex SOC. · Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration · Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem · Experience in End-to-End DFX flow development/creation. · Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation. · Strong EDA tools experience (Tessent, Design Compiler, Spyglass,) · Proficient in doing basic unit-level verification using simulations. · Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required. · Exposure to Static timing analysis & Timing closure is required. · Scan/ATPG patterns & test flows development, debug, test, and characterization · Excellent hands-on debug skills and scripting skills are critical. · Strong communication skills and the ability to collaborate effectively within a global team environment are essential. · Strong problem-solving skills · Knowledge & experience of low power concepts, clock gating, power gating is a plus · Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: · B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves leading the DFX design architecture and implementing cutting-edge features like SCAN, ATPG, and MBIST for next-generation silicon. The engineer will collaborate with RTL, verification, and PD teams to ensure correct DFT implementation and successful post-silicon bring-up.