SOC Design Engineer – RTL design and Integration at Intel - Dubai

Hillsboro, Oregon, United States -

Full Time

Start Date

Immediate

Expiry Date

27 Jun, 26

Salary

172860.0

Posted On

29 Mar, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Integration, Logic Design, RTL Coding, Simulation, CPU IP Block, Architecture Definition, Microarchitecture, Power Optimization, Performance Optimization, Area Optimization, Timing Goals, Physical Implementation, Verification Plan, UPF Design, Clock Domain Crossings

Industry

Semiconductor Manufacturing

Description

Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure highquality integration of the CPU block. Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Bachelor's degree in electrical engineering, Computer Engineering or related field with 3+ years of relevant experience, OR Master's degree Electrical Engineering, Computer Engineering or related field with 2+ years of relevant experience The relevant experience would include one of the following areas: RTL and UPF design of complex microarchitectures Microarchitect for SoC or CPU features Knowledge of Clock domain and reset domain crossings, design power considerations, design clocking considerations Preferred Qualifications: 6+ years of experience in RTL design or integration using industry EDA tools. Product development and delivery on leading edge process nodes Experience in Python programming language Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process Discover your place in our world-changing work.

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Responsibilities

The engineer develops logic design, RTL coding, and simulation for a CPU to generate cell libraries and functional units for full chip integration. This role involves active participation in defining architecture and microarchitecture features while optimizing logic for power, performance, area, and timing goals.