SoC Design Verification Engineer at Intel - Dubai

Bangalore, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

05 May, 26

Salary

0.0

Posted On

04 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

System Verilog, OVM/UVM Methodology, SoC Verification Plans, Test Benches, RTL Debugging, Simulation Models, Coverage Metrics, Regression Management, CPU/GPU Architectures, Constrained Random Verification, Python Scripting, UPF/Low Power Verification, Security Activities Integration, Synopsys Tools, Microarchitecture Specification

Industry

Semiconductor Manufacturing

Description

Job Details: Job Description: As a SoC Design Verification Engineer at Intel, you will play an integral role in ensuring the functionality, performance, and quality of cutting-edge System-on-Chip (SoC) designs. You will contribute to the development of next-generation technologies by performing meticulous verification of complex SoCs, collaborating with interdisciplinary teams, and driving innovative solutions to meet design specifications. Your work will directly influence the success and reliability of Intel's industry-leading products, empowering customers worldwide and shaping the future of technology. Key Responsibilities - Develop and execute scalable, reusable block, subsystem, and SoC verification plans, ensuring coverage and adherence to microarchitecture specifications. - Design and maintain test benches and verification environments for functional logic verification and validation. - Execute simulation models to analyze performance and uncover bugs. - Debug issues in the presilicon environment, implement corrective measures, and replicate, root cause, and resolve failing tests. - Collaborate with architects, RTL developers, and design teams to improve verification strategies for advanced architectural and microarchitectural features. - Conduct technical reviews of verification plans and proofs with design and architecture teams. - Incorporate security activities within test plans, including regression and debug tests, ensuring comprehensive security coverage. - Maintain and refine existing functional verification infrastructure and methodology to enhance validation efficiency. - Absorb learnings from postsilicon development, update test plans for missing coverages, and proliferate improvements to future products. Qualifications: Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 7+ years of experience with a Bachelor's degree or 5+ years of experience with a Master's degree. - System Verilog programming with proficiency in OVM/UVM methodology. - Developing and executing test plans for SoC verification. - Enabling and managing regressions while maintaining quality of validation (QoV) with thorough coverage metrics. - Debugging module-level or SoC-level RTL failures in simulation or emulation environments. - Familiarity with CPU/GPU architectures. Preferred Qualifications - Experience in Xeon CPU Pre-Silicon or Post-Silicon validation. - UPF/Low Power Verification Experience - Expertise in constrained random verification methodologies. - Skill in developing validation test suites and driving continuous improvements in test methodologies. - Knowledge of scripting languages such as Python for automation and efficiency enhancements. - Proficiency with Synopsys simulation and coverage tools. - Strong problem-solving abilities, effective communication skills, and a collaborative mindset. Join us in driving innovation and creating world-class technology solutions. Apply now to be part of a team that's engineering a brighter future. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process Discover your place in our world-changing work.

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Responsibilities

The engineer will develop and execute scalable verification plans for block, subsystem, and SoC levels, ensuring coverage and adherence to microarchitecture specifications. Key tasks include designing test benches, executing simulations, debugging RTL failures in presilicon environments, and collaborating with design teams to improve verification strategies.