SOC Design Verification Engineer

at  Synergent Tech Solutions

Remote, Oregon, USA -

Start DateExpiry DateSalaryPosted OnExperienceSkillsTelecommuteSponsor Visa
Immediate30 Apr, 2025Not Specified01 Feb, 20255 year(s) or aboveGit,Emulation,Pcie,Computer Engineering,Ddr,Python,Root Cause,Code Coverage,Perl,Tcl,Scratch,Scripting,Ethernet,High Speed Interfaces,Computer Science,MlNoNo
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Description:

Job Description: SOC Design Verification Engineer
Location: Redmond, WA
Hybrid (Remote option allowed)

Minimum Qualifications

  • Track record of ‘first-pass success’ in ASIC development cycles.
  • Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
  • 8 to 10 years of hands-on experience in SystemVerilog/UVM methodology
  • Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation.
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.

Preferred Qualifications

  • Experience verifying GPU/CPU designs.
  • Experience in development of UVM based verification environments from scratch.
  • Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.
  • Experience with revision control systems like Mercurial(Hg), Git or SVN.
  • Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet.
  • Experience working across and building relationships with cross-functional design, model and emulation teams.
  • Define and implement SoC verification plans, build verification test benches to enable sub-system/SoC level verification.
  • Develop functional tests based on verification test plan.
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

UVM/SV (Priority: 1)
Python/TCL/Perl (Priority: 3)
Synopsys/Cadence EDA Design/Verification tools (Priority: 1)
Job Type: Contract
Pay: $55.00 - $60.00 per hour

Benefits:

  • 401(k)
  • 401(k) matching
  • Dental insurance
  • Health insurance
  • Life insurance
  • Paid time off
  • Vision insurance

Experience:

  • GPU/CPU designs.: 5 years (Required)
  • AI/ML and Networking designs.: 5 years (Required)

Work Location: Remot

Responsibilities:

Please refer the Job description for details


REQUIREMENT SUMMARY

Min:5.0Max:10.0 year(s)

Information Technology/IT

Engineering Design / R&D

Information Technology

Graduate

Computer science computer engineering relevant technical field or equivalent practical experience

Proficient

1

Remote, USA