SoC DRAM Memory Subsystem Validation Engineering Program Manager at Apple

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

13 Mar, 26

Salary

0.0

Posted On

13 Dec, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SoC DRAM Memory Design, Validation, Architecture, Test/Product Engineering, High-Performance Memory Subsystem, DDR Controller, PHY Design, High-Speed IO Interface, DRAM Device, Calibration, Debugging Skills, Crisis Management, Project Development, Leadership Skills, Team Collaboration, Technical Discussions

Industry

Computers and Electronics Manufacturing

Description

Come and join the team that crafts Apple's groundbreaking silicon. Apple makes the greatest SoCs in the world; to do that takes thousands of employees, multiple years, and very significant R&D spending. To make the best use of those employees, time and money requires excellent methodologies and structures. As we continue to expand and mature, the processes used to develop these SOCs must be improved. Join us to do your life’s best work in this rare opportunity to help define the next big thing that will surprise and delight the world! DESCRIPTION The SoC DRAM Memory Subsystem Validation and Debug Program Manager will drive the memory subsystem readiness for our custom SoCs. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. The charter will include managing bring-up, validation, and the complicated debug of our groundbreaking memory subsystem. The EPM will also help craft the DRAM industry’s mobile roadmap and drive innovative DRAM technologies to accompany SoC’s across Apple’s product lines. In this multifaceted role, you will be the critical interface between Apple’s DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams to ensure these sophisticated memory technologies are delivered from architecture to mass production to Apple’s industry leading quality standards. MINIMUM QUALIFICATIONS BS + 10 years of relevant experience Prior experience in SOC DRAM Memory Design, Validation, Architecture or Test/Product Engineering. PREFERRED QUALIFICATIONS Knowledge of high-performance memory subsystem, including SoC memory architecture, sophisticated DDR controller, PHY design and high-speed IO interface, DRAM device, and associated calibration/training mechanisms. Experience shipping high volume DRAMs / SoCs. Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus. Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management. Excellent debugging skills. Proven track record to drive resolution of critical problems, while under pressure. Ability to understand complex technical discussions and extract action plans. Passionate to own/drive project development using well-defined metrics. Thrives in dynamic schedule driven development environment. Ability to succinctly summarize complex details for executive reporting. Extraordinary leadership skills and ability to encourage team members with a dedication to see the bigger picture Phenomenal leadership and social skills with a reciprocal approach.

Responsibilities

The SoC DRAM Memory Subsystem Validation and Debug Program Manager will manage the readiness of the memory subsystem for custom SoCs, overseeing bring-up, validation, and debugging. This role involves interfacing with various teams to ensure the delivery of sophisticated memory technologies to meet Apple's quality standards.