SOC Intergration Engineer at MatX

Mountain View, California, United States -

Full Time

Start Date

Immediate

Expiry Date

26 Aug, 26

Salary

600000.0

Posted On

28 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SystemVerilog, Python, Perl, SOC Integration, RTL Design, UCIE, Design Synthesis, Linting, Clock & Reset Domain Crossing, Timing Constraint Validation, Logical Equivalency Verification, DFT Wrappers, Emulation Platforms, Verification Methodologies, Physical Design Collaboration, AI-driven Automation Tools

Industry

Computer Hardware Manufacturing

Description

What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design. Partner with SubSystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) Top-level RTL. Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL. Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL. Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams. Define and support SoC-level timing constraints, ensuring rigorous validation against Subsystem design and physical design requirements. Provide technical support to package and board teams by defining SOC pin requirements and facilitating the generation of interposer netlists. Who You Are Demonstrate proficiency in SystemVerilog and scripting languages such as Python or Perl to drive chip design RTL and associated flows. Possess a proven track record in integrating high-performance computing elements (CPUs, GPUs, accelerators) and high-speed interconnect standards like UCIE, while managing memory and logical functionalities within the SOC RTL. Apply working knowledge of logical equivalency verification for SOC-level subsystem interfaces, collaborating with physical design teams to incorporate floorplan requirements into the RTL. Manage memory wrapper generation, including the integration of DFT wrappers into Subsystem RTL. Provide automation support for generating and configuring SOC RTL with user-defined Subsystems for Design Verification (DV) purposes. Leverage hands-on experience with AI-driven tools to architect automation for SOC integration and facilitate technical support for cross-functional implementation teams. Utilize hands-on experience with design synthesis, linting, clock & reset-domain-crossing, and timing constraint validation to ensure high-quality SOC sign-off. Familiarity with emulation platforms and verification methodologies is highly desirable. Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation. Early Career - $120,000 - $275,000 + equity Mid Career - $175,000 - $450,000 + equity Senior Career - $275,000 - $600,000 + equity What We Offer A Stake in our success A cash/equity mix that fits your needs and option to do early exercise Health & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t) Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities Team Connection Team Lunches, quarterly off-sites, and regular town halls Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t! Flexible Spending Accounts Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses Commute On Us For those commuting up to 1 hour, put your rideshare cost on our company card and reclaim the drive-time to get work done! MatX E[x]tras $50 per month to use on the perks you care about most Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi expense reimbursement As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances. All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays. This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities. MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.

Responsibilities

Drive the evolution of silicon architecture-to-design methodology by engineering scalable solutions for full-chip SOC RTL integration. Collaborate with cross-functional teams to establish clock/reset methodologies and define SOC-level timing constraints.