SoC Packaging Engineer at Apple

Taipei, , Taiwan -

Full Time

Start Date

Immediate

Expiry Date

12 Jun, 26

Salary

0.0

Posted On

14 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Ic Packaging, Materials Science, Chemistry, Chemical Engineering, Organic Materials, Polymers, Molding Compounds, Under-fill, Thermally Conductive Adhesive, TIM, Mcm Package Technologies, Micro Bump Plating, Rdl Lithography, Hbm Integration, Beol, Device Physics

Industry

Computers and Electronics Manufacturing

Description

At Apple, we believe our products begin with our people. By hiring a team with varied strengths, we drive creative thought. By giving that team everything they need, we drive innovation. By hiring incredible engineers, we drive precision. And through our collaborative process, we build memorable experiences for our customers. These elements come together to make Apple an amazing environment for motivated people to do the greatest work of their lives. You will become part of a hands-on development team that sets the standard in cultivating excellence, creativity and innovation. Will you help us design the next generation of revolutionary Apple products? DESCRIPTION We are looking for a senior level IC packaging engineer to develop exciting new products. Your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies. We are looking for individuals who are very innovative with a proven track record to bring packaging solution from concept to high-volume manufacturing. MINIMUM QUALIFICATIONS M.S or Ph.D. degree in materials science, chemistry, chemical engineering or similar disciplines with a minimum of 5 years of experience in IC packaging. In-depth knowledge in organic materials (polymers, molding compounds, under-fill, thermally conductive adhesive/TIM,..,etc) for large body size MCM package technologies. PREFERRED QUALIFICATIONS Good understanding to organic package process & material characterization such as micro bump plating, RDL lithography, molding compound and under-fill. Knowledge in HBM integration and reliability characterization, advanced silicon node BEOL and device physics or component/board level reliability testing are plus. Proven track record to drive issue resolution with good understanding to root cause and physics, motivate and mobilize all levels within supplier to accomplish any given task. Able to perform independent research and development work with minimal supervision. Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at internal or external meetings.

Responsibilities

The engineer will interface between internal design, quality, supply chain, and external suppliers to develop and deploy new IC packaging technologies for next-generation products. This role requires bringing packaging solutions from the initial concept phase through to high-volume manufacturing.