Join a cutting-edge and well-funded hardware startup in Silicon Valley as a SoC Performance Architect. Our mission is to reimagine silicon and create RISC-V based accelerated computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.
Rivos SoC Performance team is seeking highly motivated candidates to perform performance modeling and verification activities for Rivos SoCs. The primary role is to engage in performance verification of pre-silicon and post-silicon server compute silicon.
We are looking for all levels of talent, from entrance to advanced level of experience.

REQUIREMENTS

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• Proficient in SystemVerilog and waveform debugging tools.

• Knowledge of SW programming with good understanding of C/C++, Python, and modular object oriented software development.
• In-depth knowledge of memory subsystem architecture, microarchitecture and design including caches, cache coherency, NOC, LPDDR/DDR/HBM, PCIe/CXL, Ethernet and IO.
• Strong knowledge in SoC architecture and power/performance trade-offs.
• Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
• Ability to work collaboratively in a team and be productive under aggressive schedules.

EDUCATION AND EXPERIENCE

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• Bachelor’s degree plus 5 years of industry experience.

• Master’s degree plus 3 years of industry experience.
• Ph.D with internship experience.

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• As a SoC Performance Modeling and Verification Engineer, you will own or participate in the following:

• Validate the performance model and RTL against the specification and correlate the performance model with RTL
• Develop performance verification test suite and infrastructure to ensure quality of model and design
• Creating traces for SystemVerilog/UVM based testbenches and performance model
• Hands on debugging of performance issues and adding features for transactors in these testbenches
• Work with architecture and design teams to determine performance targets and configurations, and review results
• Provide feedback to the architecture and design teams regarding the micro-architectural choices that may have been made