Meta’s Reality Labs(RL) focuses on delivering Meta’s vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.As an SoC Physical Design Engineer at Meta Reality Labs, you will perform physical design implementation of complex SoC and IP-subsystems. In this high impact role, you will work closely with cross functional teams to ensure our custom silicon developments meet the challenging power, performance and area requirements needed for our wearable products.

MINIMUM QUALIFICATIONS:

• 3+ years of hands-on experience in ASIC physical design with solid understanding of digital design fundamentals
• Fluent in scripting languages such as TCL, Perl, or Python for flow automation
• Experienced in cross-functional communication and collaboration

PREFERRED QUALIFICATIONS:

• Experience with low-power design techniques
• Proficient in STA, clock tree synthesis and IR drop analysis
• Knowledge of MBIST, Scan implementation and tradeoffs for physical convergence
• Experience with advanced process nodes (7nm or below)

• Physical design implementation from RTL to netlist for complex digital blocks or full-chip designs, responsible for floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis and signoff
• Collaborate with RTL design, DFT, verification, and power teams to ensure seamless integration and secure QOR
• Optimize for power, performance, and area (PPA) using industry-standard tools and methodologies
• Contribute to automation of physical design flows and improve design productivity