SoC Physical Design Engineer, Power Grid at Apple

Waltham, Massachusetts, United States -

Full Time

Start Date

Immediate

Expiry Date

09 Mar, 26

Salary

0.0

Posted On

09 Dec, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, Automation, Tcl, Python, CAD, Physical Verification, Electrical Analysis, PnR, Power Grid, Voltage Drop Analysis, STA, Layout Verification, ASIC Integration, Floorplanning, Clock Distribution, I/O Planning

Industry

Computers and Electronics Manufacturing

Description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role, we work within a team environment responsible for completing partition place and route from netlist to tapeout including automation tasks for Apple SoC! DESCRIPTION - Experience with automation for Physical Design, for block execution and experience in automation using tcl and/or python. - Work multi-functionally with CAD/Physical Verification/Electrical analysis and PnR Teams to ensure strong and drc clean power grid. - Develop features and methodology solutions to be used by wide range of SOC partitions. - Collaborate with technology teams for node evaluations, global PD engineers, and physical verification and electrical analysis teams. - Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. - Work with the cross functional teams to drive methodologies and “best known methods” to streamline physical design work. Come up with guidelines and checklists, drive flow development and deployment. MINIMUM QUALIFICATIONS Minimum BS and 10+ years of relevant industry experience. Familiar with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration. Experience with scripting and programming skills, ability to write maintainable and reusable scripts/programs of medium complexity in suitable languages (TCL/Python). Understanding of industry standard tools for PNR, Voltage Drop Analysis, STA & Layout Verification. PREFERRED QUALIFICATIONS Experience with automation for Physical Design, block level execution and experience. Experience of cross-functional collaboration with CAD/Physical Verification/Electrical analysis and PNR Teams to ensure electrically robust power grid. Experience with latest technology nodes tapeout is a plus. Knowledge in Power Grid Design and/or Voltage Drop Analysis is a plus.

Responsibilities

The role involves completing partition place and route from netlist to tapeout, including automation tasks for Apple SoC. The engineer will collaborate with various teams to ensure a clean power grid and resolve design issues.