SoC Physical Design Engineer, STA/Timing at Apple

Sunnyvale, California, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Dec, 25

Salary

0.0

Posted On

21 Sep, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

STA, Timing Closure, Perl, TCL, ECO Techniques, Circuit Modeling, SPICE Models, Noise, Crosstalk, OCV Effects, Documentation, Timing Analysis, Physical Design, Methodologies, Design Debugging, Timing Infrastructure

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product. In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology. DESCRIPTION - Work with design teams to understand and debug constraints and facilitate logic changes to improve timing. - Work with the Physical Design team, highlighting issues and best practices. - Help create timing ECO’s for project tapeout. - Create and maintain scripts and methodologies for analysis and runs. - Create documentation and help with guidelines/specs. - Deep analysis of timing paths to identify key issues. - Implement timing infrastructure. MINIMUM QUALIFICATIONS Minimum BS and 3+ years of relevant industry experience. Experience with large design STA and Timing Closure. Programming skills with Perl and TCL. PREFERRED QUALIFICATIONS Hands-on experience in STA. Familiar with important aspects of timing of large high-performance SoC designs in sub-micron technologies. Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others. Familiar with circuit modeling, including SPICE models, and worst-case corner selection. Familiar with ECO techniques and implementation. Good communicator who can accurately describe issues and follow them through to completion.

Responsibilities

You will be responsible for the physical implementation of design partitions for a complex SoC. This includes working with design teams to debug constraints, creating timing ECOs, and maintaining scripts for analysis.