SoC Physical Design Methodology Engineer at Apple

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

08 Jul, 26

Salary

0.0

Posted On

09 Apr, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical design, SoC design, Electrical analysis, Power delivery, Static timing analysis, Spice simulations, Python, Tcl, Interconnects, Parasitic extraction, Performance analysis, Data science, Machine learning, Signoff flows, Circuit design, Advanced technology nodes

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! Come help us design the next generation of revolutionary Apple products. We're looking for a forward-thinking and unusually talented engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft and implement methodologies with a high impact on upcoming products that will delight and inspire millions of Apple’s customers every single day. In this role, you'll be directly involved in our physical design methodology efforts, collaborating right alongside our internal multi-functional teams to ensure our SoCs achieve the optimal power, performance, and area (PPA) in the most efficient way possible. We account for every nanowatt, every nanometer, and every picosecond from theory to silicon. DESCRIPTION As a Physical Design Methodology engineer you will be an active participant in the team responsible for ensuring our physical design methodology is efficient, robust, and reliable. You will create and implement methodologies that improve the robustness, power, performance, and area (PPA) of our on-chip interconnects. You will perform electrical analysis to understand how physical effects impact the performance of our designs. You will develop construction methodologies to help mitigate any PPA degradation found in silicon. You will help ensure our modeling of silicon is efficient and accurate by running our signoff flows and comparing results to measurements from silicon we create. You will collaborate with the standard cell team to identify new cells to improve PPA, yield, or engineering productivity. You will be working with CAD and design teams to drive these improvements and updates in our production design flows in an effective and timely manner. You will verify theories by creating a strategy to verify them in silicon. You will apply the latest advances in data science and machine learning when needed in crafting these methodologies. MINIMUM QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Computer Science, or related field with 3 years of experience. PREFERRED QUALIFICATIONS Have a strong intellectual curiosity, with excellent communication skills. Organized, a self-starter, and adaptable to any challenge that comes up. Physical design experience on SoC designs is a plus. Have experience in working with advanced technology nodes. Deeply knowledgeable about interconnects, parasitic extraction, performance analysis, and how manufacturing effects make these non-ideal. Have an extensive knowledge of power delivery and how power-supply noise impacts chip performance. Understand inductance effects and have circuit design experience. Are very comfortable running and modifying Spice simulations. Familiar with static timing analysis tools and methodologies. Being able to explain silicon behaviors should be an Have a proven understanding of scripting languages such as Python and Tcl. Experience with flow development for a large number of users on a tight schedule is a plus.

Responsibilities

You will craft and implement physical design methodologies to optimize SoC power, performance, and area. This involves collaborating with multi-functional teams to drive improvements in production design flows and verifying silicon behaviors.