SoC Power Analysis Engineer- PTPX/Low Power Physical Design at Advanced Micro Devices, Inc

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

24 May, 26

Salary

0.0

Posted On

23 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Power Analysis, PTPX Flow, Physical Design, ICC, Fusion Compiler, Innovus, Battery Life Workloads, Verilog, System Verilog, C++, C, Fsdbs, VCS Simulation, Formality Endpoint Mapping, Perl, Python

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The focus of this role is to analyze power consumption of SOC for different use cases and identify optimization opportunities, generate power optimal recipe for physical design teams, help design teams build power optimal design at architecture level, RTL level. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and low power design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the use cases for which design need to be optimized, power features being implemented. Build test plan documentation, for sub-set of use case tests work with simulation teams to get required fsdb for power analysis and optimize design. Run PTPX to generate power numbers, analyze power consumption, correlate the power with older project or IP level power projections. Analyze power consumption in design, identify ways implement a power optimal design, share recepie with physical design teams. PREFERRED EXPERIENCE: Proficient in Power analysis and PTPX flow with 7+ years of exp Proficient in power optimal design implementation at Physical design stage Proficient in using physical design flows, ICC, Fusion compiler, Innovus Experienced in battery life workloads and analysis, test definition for power usecases Experienced with Verilog, System Verilog, C, and C++ Experience using fsdbs, vcs simulation, formality endpoint mapping Experience with scripting languages perl, python, etc.. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role focuses on analyzing System on Chip (SOC) power consumption across various use cases to identify optimization opportunities and generate power-optimal recipes for physical design teams. This involves collaborating with architects and engineers to build power-optimal designs at the architecture and RTL levels.