Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As a SOC Verification Engineer, you will be responsible for pre-silicon RTL verification of block and top-level SOC. With deep understanding of SOC architecture and meticulous attention to details, you will interact with all disciplines to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

DESCRIPTION

As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all fields: • Understand details of different types of architecture, industry-standard low power architecture, and build block / chip level testbench using best-in-class verification methodology. • Create detailed verification plan from specification and in coordination with architects. • Develop reusable block/IP level test bench and support IP integration verification. • Generate directed and ingenuous constrained random tests. • Create/analyze coverage model and enhance testbench/test to increase coverage. • Build automated flows for block and chip level verification. • Debug failures, manage bug tracking, and close coverage. • Hold detailed verification reviews and set standard for coding quality. • Work closely with team members to improve methodology and flow.

MINIMUM QUALIFICATIONS

• BS with 3+ years relevant experience.
• Experience in HVL and HDL (System Verilog, Verilog).
• Knowledge of HVL methodology (UVM/OVM/VMM).
• Solid verification skills in problem solving, constrained random testing, and debugging.
• Solid understanding of reusable verification framework.
• Knowledge of digital logic design, chip architecture and microarchitecture.
• Great teammate with excellent communication skills and the desire to take on diverse challenges.

PREFERRED QUALIFICATIONS

• Knowledge of industry standard interfaces.
• Experience with System Verilog Assertion (SVA).
• Experience with IP verification method and integration verification.
• Knowledge with IPs developments and release flow.
• Programing experience in C.
• Experience writing scripts in languages such as Perl or Python.
• Programming experience in C++ and assembly.
• Experience with embedded CPU verification.
• Experience defining coverage space and writing coverage model.
• Experience with low power verification.
• Knowledge of wireless protocols like Bluetooth and WiFi.
• Experience with formal verification tool (JasperGold or others).

Please refer the Job description for details