Soft IP Design Engineer at LATTICE SEMICONDUCTOR CORPORATION

George Town, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

28 May, 26

Salary

0.0

Posted On

27 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, SERDES, DisplayPort, HDMI, MIPI, SDI, SPI, I2C, I3C, CDC, Lint, Verification, Debug, Timing Closure, Verilog, SystemVerilog

Industry

Semiconductor Manufacturing

Description

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Job Description We are seeking a Soft IP Design engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The individual should have the ability to work closely with architect to translate specifications into high-speed RTL design, for the best Performance, Power and logic utilization. Requirements Key Skills Experience in high speed SERDES and video protocols (e.g.: DisplayPort, HDMI, MIPI, SDI) or Peripherals (SPI, I2C or I3C) is a plus. Hands-on experience in FPGA RTL design, CDC/lint, verification, debug and timing closure is preferred. Programming skills (e.g.: Verilog, SystemVerilog, C/C++, Perl, TCL or Python). Experience in hardware validation or hardware interoperability test. Experience in soft IP packaging, example design and testbench development will be an added advantage. Education and General: BS/MS/PhD in Electronics or Computer Engineering minimum of 7 years of FPGA IP design experience. Independent and self-motivated, capable of executing under dynamic environment and uncertainties.

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Responsibilities

The engineer will be responsible for building Connectivity IP portfolios for Lattice FPGAs, working closely with architects to translate specifications into high-speed RTL designs. The goal is to optimize for performance, power consumption, and logic utilization.