QUALIFICATIONS:

• BS or MS in Electrical Engineering with 5+ years’ experience in Power IC design
• Expert-level proficiency with Cadence Virtuoso and verification tools
• Strong understanding of analog layout techniques: device matching, noise isolation, current density, and thermal awareness
• Strong sense of ownership/accountability; able to work independently and collaboratively in a team environment.
• Experience with FinFet layout is desirable
• Good communication skills (verbal, written)

ROLE OVERVIEW

To expand the team in Munich we are seeking an experienced Analog/Mixed-Signal layout Engineer to contribute to the development of high-performance power management ICs in advanced CMOS nodes. In this role, you will collaborate closely with circuit designers to deliver high-density, ultra efficient layout implementations that meet aggressive performance and size targets.
The ideal candidate has 5-10 years of hands-on experience, deep expertise in custom analog layout, and thrives in a startup-like, high-accountability culture.

KEY RESPONSIBILITIES

• Execute full-custom layout of analog/mixed-signal building blocks including LDOs, bandgaps, opamps, comparators, and switching regulators
• Floorplan and implement top-level analog/mixed-signal blocks with attention to matching, shielding, routing symmetry, and parasitic
• Perform physical verification: DRC, LVS, ERC using industry standard tools
• Collaborate with designers to iterate and optimize layouts based on circuit sensitivities and extracted simulation results
• Ensure reliability and manufacturability through proper layout practices