Sr. ASIC Design Engineer (Silicon Engineering) at SpaceX

Irvine, California, United States -

Full Time

Start Date

Immediate

Expiry Date

19 Mar, 26

Salary

220000.0

Posted On

20 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Implementation, Verilog, System Verilog, ASIC Design, FPGA Development, Timing Closure, Scripting, EDA Tools, Power Optimization, Multicore CPU Design, Bus Protocols, Embedded Processors, High Speed Design, Low Power Design, Problem Solving, Team Collaboration

Industry

Aviation and Aerospace Component Manufacturing

Description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Evaluate architectural trade-offs based on features, performance requirements and system limitations Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design Work closely with verification team to ensure all aspects of the design are covered and verified Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check) Participate in silicon bring-up and validation BASIC QUALIFICATIONS: Bachelor’s degree in electrical engineering, computer engineering, or computer science 5+ years of experience in RTL implementation PREFERRED SKILLS AND EXPERIENCE: Ability to solve complex problems including clock domain crossings and power optimization ASIC/SoC system integration experience Experience with multicore CPU subsystem design Experience with standard bus protocols (e.g. AXI, AHB, etc.) Experience with embedded processors Experience with high speed and low power design techniques Scripting skills (Python, TCL etc.) Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II) Ability to work in a dynamic environment with changing needs and requirements Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis Enjoys being challenged and learning new skills ADDITIONAL REQUIREMENTS: Must be willing to work extended hours and weekends as needed COMPENSATION & BENEFITS: Pay range: ASIC Design Engineer/Senior: $160,000.00 - $220,000.00/per year Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here. SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

Responsibilities

The engineer will evaluate architectural trade-offs, define micro-architecture, and implement RTL designs while ensuring verification and timing constraints. They will also participate in silicon bring-up and validation.