Sr Design Verification Engineer at Qorvo

Richardson, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

26 Sep, 26

Salary

0.0

Posted On

28 Jun, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Verification, DRC/LVS, PDK Development, Siemens Calibre, Synopsys IC Validator, Cadence Pegasus, Scripting, Semiconductor Fabrication, Rule Writing, Automation Workflows, Compound Semiconductors, Tape-out Flow Management

Industry

Semiconductor Manufacturing

Description

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet. Job Summary We are seeking an experienced Engineer to bridge the gap between design teams, technology development, and manufacturing reality. In this role, you will act as the ultimate quality gatekeeper. You will define, validate, and enforce physical layout rules (DRC/LVS) and automation software code used across multiple engineering groups. Your work will directly ensure first-time-right layouts and optimal yield by auditing deliverables from internal teams and external vendors. You will support the implementation of new technologies that are under development and continuous improvement of existing technologies for Qorvo, Inc. Key Responsibilities: Layout & Physical Verification Enforce sign-off compliance across all design groups using physical verification tools. Evaluate and test Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Process Development Kit (PDK) decks as well as mask automation code and other internal coding systems. Review complex layout fixes with design and technology teams to resolve issues. Collaborate with other teams to interpret and implement advanced process design kit (PDK) layout rules. Software, Automation & Methodology Audit and validate internal software scripts, code infrastructure, and automation workflows. Build automated regression tests to ensure multi-group deliverables do not break the overall tape-out flow. Develop Golden Standards for new and existing technologies to ensure quality of code. Create unified design methodologies to standardize how different teams write code and handle layouts. Provide technical support and tool training to logic design, physical design, and layout teams. Required Qualifications: Education & Experience Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or related field 5+ years of experience in semiconductor physical verification, CAD, or design automation. Experience in compound semiconductors such as GaN, GaAs, pHEMT, transistors is a plus. Technical Skill Set Industry Standard Tools: Deep hands-on experience with Siemens Calibre (DRC/LVS), Synopsys IC Validator, or Cadence Pegasus. Scripting & Software: Advanced proficiency in scripting to automate verification flows. Semiconductor fabrication knowledge: Familiarity with semiconductor processes and technology development methodologies. Rule Writing: Proven ability to read, write, and debug runsets and verification rule decks. Preferred Qualifications Experience auditing cross-functional teams or managing multi-site tape-out flows. Familiarity with revision control systems Strong communication skills to negotiate layout trade-offs and code quality standards with diverse engineering teams. This position is not eligible for visa sponsorship by the company #LI-SM1 MAKE A DIFFERENCE AT QORVO We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us. We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.

Responsibilities

The role involves defining and enforcing physical layout rules (DRC/LVS) and validating automation software to ensure first-time-right layouts. The engineer will audit deliverables from internal and external teams while supporting the implementation of new semiconductor technologies.