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Sr. DFX Architect at Ericsson
Austin, Texas, United States -
Full Time

Start Date

Immediate

Expiry Date

05 Feb, 26

Salary

0.0

Posted On

07 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

DFX Standards, ATPG, Scan, JTAG, iJTAG, BIST, SOC Level DFT Planning, Architecture, Execution, Automation, Infrastructure, Post Silicon Debug, Yield Bring Up, Test-Time, Pattern Delivery, Physical Design Implementation

Industry

Telecommunications

Description
Must have working knowledge about DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs between test quality, test time, efficiency, and their impact to overall design implementation. Experience with SOC level DFT planning, architecture, and execution. Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function. Experience with post silicon debug, yield bring up, test-time and pattern delivery while working closely with TEPE teams for long term strategic improvements. Continuous drive to improve flows, methodology and architecture for enabling scalability of the overall team in years to come. Understanding of Physical design implementation flows and methods to enable a smooth integration of DFT in the design with efficient and quality hand offs. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. We truly believe this approach drives innovation, which is essential for our future growth. DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned. Primary country and city: USA || Austin, TX Job details: Developer Recruiter name: Jim Everett
Responsibilities
The Sr. DFX Architect will focus on DFX standards and practices, ensuring efficient execution pipelines within the DFX function. The role involves post-silicon debug and collaboration with TEPE teams for strategic improvements.