Sr. Engineer, Verification at SiTime Corporation

Minato-ku, Tokyo, Japan -

Full Time

Start Date

Immediate

Expiry Date

27 Mar, 26

Salary

0.0

Posted On

27 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SystemVerilog, UVM, Scripting Languages, Perl, Python, SystemVerilog Assertions, Analog Schematic, Cadence Virtuoso, Digital Design, Verilog, Mixed-Signal Verification, C++, Functional Models, Formal Property Verification, Datapath Designs, Filters

Industry

Semiconductor Manufacturing

Description

About SiTime SiTime Corporation is the precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com [https://www.globenewswire.com/Tracker?data=KZboO_E5KYNf2nXu9snYUrujcxPVV14r8VUqaw-krQjviK4SVzg-T3gX0Yv8pdrIU2yKG5VITW08WA-AWCTQKQ==]. Job Summary As a Sr. Verification Engineer, you will be part of a team developing MEMS timing ICs. It is not necessary to meet all job requirements to be a qualified candidate for the position. Responsibilities: * Developing SV-RNM models for both analog and mixed-signal circuits * Developing verification plan from chip or block specifications * Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.) * Developing digital-top verification in System Verilog * Defining and writing System Verilog Assertions (SVA) * Defining and writing functional coverages and covergroups * Running simulations and debugging simulation results * Reviewing verification results for Tape-out sign-off * Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas Minimum Requirements: * MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry * Good verbal and written communication skills in English * Proficient in SystemVerilog and SystemVerilog OOP * Fluency in utilizing scripting languages such as Perl / Python * Proficient (through work experience) in verification using UVM * Strong experience writing SystemVerilog Assertions (SVA) * Understanding of Analog schematic and experience with Cadence Virtuoso * Basic understanding of digital design using Verilog * Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers * Ability to work independently and drive solutions to challenging problems Desired Qualification: * Experience with generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques * Experience with UVM-AMS methodology * Solid experience with Formal Property Verification (FPV) * Programming experience writing OOP code in C++ * Excellent written and verbal communication skills in English * Experience with performing analog mixed-signal verification * Proven track record in working well with others in fast-paced and collaborative work environment * Knowledge of analog design * Knowledge of synthesizable digital design * Experience working on verification of datapath designs including filters In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success. SiTime is an Equal Opportunity Employer [http://www.sitime.com/images/EEO-is-the-law.pdf]. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. Learn More about SiTime: Review the Get to Know SiTime [https://www.sitime.com/company/careers] section of our career page to explore our culture, values, and what makes us unique. * Innovation on Top – Philosophies of Innovation with Rajesh Vashist [https://www.innovatorsontap.com/podcast/the-philosophy-of-innovation-w-rajesh-vashist] * Fabrication Knowledge – An Interview with Rajesh Vashist [https://www.fabricatedknowledge.com/p/an-interview-with-rajesh-vashist-3e0#details] * SiTime Corporation – YouTube [https://www.youtube.com/user/sitimecorp/videos]

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Responsibilities

The Sr. Verification Engineer will develop SV-RNM models for analog and mixed-signal circuits and create a verification plan based on specifications. They will also run simulations, debug results, and communicate with stakeholders to ensure effective teamwork.