Sr Manager, Physical Design at Renesas Electronics

Noida, Uttar Pradesh, India -

Full Time

Start Date

Immediate

Expiry Date

05 Jun, 26

Salary

0.0

Posted On

07 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Synthesis, UPF, VCLP, LEC, RTL Synthesis, DFT, Physical Design, Power Domains, RTL ECOs, TCL Scripting, Cadence Genus, Synopsys Fusion Compiler, Conformal, Low-power Design, Power-aware ECO, Physical-aware Synthesis

Industry

Semiconductor Manufacturing

Description

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Experience: 10-15 years Role Summary We are seeking Physical Design expert/manager with strong people and technical skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis ownership, LEC closure, UPF development, and VCLP sign‑off for complex SoC designs, working closely with Physical Design, DFT, and Front‑End teams. The person should have skillset for people management as well. Key Responsibilities Complete understanding of RTL to GDS flow in physical design cycle. Able to collaborate, lead and drive team members with quality and schedule in check, aligned to organizational needs. Own RTL synthesis from elaboration to final signoff. Debug design constraints and support DFT insertion. Cross team collaboration is must. Ability to handle multiple tasks (at individual and at team level) and changing priorities from internal customers. Deep debug skillset for logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists. Create, maintain, and debug UPF, ensuring alignment with FE power intent. Understand, Define and manage power domains (power switches, isolation, retention, alwayson). Support lowpower signoff (VCLP / power checks). Handle RTL ECOs during late design stages. Automate flows using TCL scripting. Lead by example technically by having a strong technical expertise in several areas of Physical Design. Qualifications Required Qualifications 10+ years of hands‑on experience in Physical design for SoC designs. Strong knowledge of RTL, synthesis optimization, and low‑power design. Hands‑on experience with UPF creation and power‑domain modelling. Experience with tools such as Cadence Genus, Synopsys Fusion Compiler, Conformal, VCLP. Strong TCL scripting skills (Perl/Python is a plus). Preferred Advanced node experience (7nm / 5nm or below). Power‑aware ECO experience. Exposure to physical‑aware synthesis and exposure to SoC‑level UPF/ VCLP closure. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Employment Type: Regular (PERM) Remote Work Available: No

Responsibilities

The role involves owning RTL synthesis from elaboration to final signoff, managing LEC closure, and developing/debugging UPF for complex SoC designs in collaboration with cross-functional teams. Key tasks include defining power domains, supporting low-power signoff, handling RTL ECOs, and automating flows using TCL scripting.