Start Date
Immediate
Expiry Date
25 Sep, 26
Salary
0.0
Posted On
27 Jun, 26
Experience
5 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
Bit Cell Layout, Pitch Matching, Row Decoder Layout, Column Decoder Layout, Cadence Virtuoso, Calibre DRC/LVS, DRAM Architecture, LPDDR Architecture, Device Physics, Transistor Matching, Parasitic Optimization, EM/ESD Reliability, AI/ML for Layout, Full-Custom Layout, Memory Array Hierarchy, Peripheral Integration
Industry
Semiconductor Manufacturing