SUMMARY

Blaize is a groundbreaking deep-learning technology company focused on making AI universally accessible to enterprises and people. Our breakthrough silicon architecture and innovative software platform empower designers to exploit the benefits of AI and lead the largest tech transformation in decades.
A skilled and experienced senior physical design engineer is required immediately to work on exciting System-on-Chip (SoC) development projects. The SoCs revolve around a number of IPs developed within the company and a range of third-party Ips, such as CPUs (ARM, RISCV), video and image processing IP, Serdes, MIPI CSI, DSI, PCIe, UCIe, DDR, Ethernet, eMMC/SD/UFS, Network-on-Chip and other peripheral IP.
The role requires a good understanding of the whole RTL2GDS flow, SoC level physical design activities and Tapeout experience of large complex designs. It will involve a variety of work including Physical design review management, checklist and signoff requirements generation, understanding third-party IP physical integration and managing third party partners to complete various aspects of the SoC physical design to the highest possible quality and on schedule. The SoC teams goal is to be able to go to production with first spin silicon.
The candidate should be able to work independently and within a team (both internal and with external partners) on complex systems and to tight timescales to meet the needs of the project. Blaize SoCs are both high performance and energy efficient so knowledge on obtaining the best PPA within physical design and implementation is required. Additionally, Blaize also works with external third-party design services partners; experience either as a customer or design service provider would be a plus. Experience with leading edge low geometry process nodes is also desirable.

EDUCATION AND EXPERIENCE

• Bachelor’s or master’s degree in Electronics, Computer Science or another relevant degree; or equivalent experience.
• Experience in RTL2GDS full design flow.
• Experience of multi-million gate ASIC designs.
• Good experience of SoC top level physical design strategies for large complex SoCs.
• Excellent STA timing constraints generation and debugging.
• Experience of High Speed SERDES (DDR/PCIe/Ethernet) physical subsystem integration.
• Strong experience in floorplanning, IP integration, checks physical/timing/electrical quality, and final signoff.
• Strong experience in synthesis and STA timing analysis.
• Experience with tools for logic synthesis, placement, CTS and routing, timing analysis, and Physical Verification design checks.
• Excellent debugging and problem-solving skills.
• Knowledge of low power physical design techniques.
• Understanding of Design for Test methodologies is a plus.
• Network-on-chip interconnects experience is a plus.
• Comfortable working in a dynamic company environment.
• Able to work independently and able to rapidly assimilate new concepts and technologies.
  Blaize is an equal opportunity employer. We pride ourselves on having a diverse workforce and we do not discriminate against any employee or applicant because of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition, or any other basis protected by law. We respect the gender, gender identity, and gender expression of our applicants and employees, and we honor requests for preferred pronouns. It is our policy to comply with all applicable national, state, and local laws pertaining to nondiscrimination and equal opportunity.

• Understand and manage Physical design requirements for all third-party IP used in SoC.
• Review and manage Physical Design flow to ensure continuous improvement.
• Generate and maintain checklists/documentation for all aspects and stages of Physical Design flow.
• Responsible for Technology Library maintenance and Memory generation.
• Provide clear and accurate documentation and reports.
• Report status and issues to the physical design manager and/or project manager.
• Occasional overseas travel may be required.