Sr Principal ASIC Design Verification Engineer (NetSec) at Palo Alto Networks

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

02 Mar, 26

Salary

260000.0

Posted On

02 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Design Verification, SystemVerilog, UVM, Python, C/C++, Debugging, Test Plans, Functional Coverage, Emulation, Silicon Validation, Networking, Cyber Security, Formal Property Verification, Self-Checking Infrastructure, Constrained-Random Testing, Metrics-Driven Verification

Industry

Computer and Network Security

Description

Company Description Our Mission At Palo Alto Networks® everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are. Who We Are We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes. Job Description Your Career As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for features, performance, and reliability. You will define verification methodologies, architect test benches, write test plans, specify coverage, write tests, and debug. You will work on diverse platforms including simulation, emulation, formal verification, and silicon validation. We expect office-based employees to be in the office four days per week, with one day working from where they choose. We believe being together facilitates casual conversations and those magic moments where we can work on issues and ideas informally. These moments build capability and deepen trusted relationships and allow our people to feel safe in taking risks and being disruptive. Like so many companies, we are working through the details and things could change …. but in general if a role is deemed office-based we want our teams to be together four days per week. Your Impact Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies Develop flows, methodologies, and infrastructure for emulation - Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers Define new tools and methodologies to continuously improve quality and velocity Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification Qualifications Your Experience BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred Minimum 5 years experience in ASIC design verification Demonstrated success in taking multiple ASIC products from concept to mass production Expertise in SystemVerilog and UVM Technical strength in the following areas is required Defining test plans, including comprehensive adversarial testing Developing rich functional coverage models Creating powerful and scalable test benches Implementing sophisticated self-checking infrastructure with reference models and scoreboards Developing reusable constrained-random tests Debugging failures Closing coverage Experience in the following areas is preferred Networking and cyber security Formal property verification Silicon validation - bringup, test, debug, and regression Creating models in Python and C/C++ Writing driver code in C Skilled in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status Strong leadership, collaboration, and communication skills Additional Information The Team Our engineering team is at the core of our products and connected directly to the mission of preventing cyberattacks. We are constantly innovating — challenging the way we, and the industry, think about cybersecurity. Our engineers don’t shy away from building products to solve problems no one has pursued before. We define the industry instead of waiting for directions. We need individuals who feel comfortable in ambiguity, excited by the prospect of a challenge, and empowered by the unknown risks facing our everyday lives that are only enabled by a secure digital environment. Compensation Disclosure The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $235000 - $260000/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here. Our Commitment We’re problem solvers that take risks and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together. We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at [email protected]. Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics. All your information will be kept confidential according to EEO guidelines.

Responsibilities

As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our next-generation firewall products meet industry-leading requirements. You will define verification methodologies, architect test benches, write test plans, and debug across various platforms.