Sr. Principal Design Engineer at Cadence Design Systems

Noida, Uttar Pradesh, India -

Full Time

Start Date

Immediate

Expiry Date

18 Sep, 26

Salary

0.0

Posted On

20 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Design Verification, UVM, System Verilog, AMBA Protocols, AXI, AHB, APB, Interconnects, NoCs, Perl, Unix Shell, Formal Verification, Gate Level Simulations, Cadence Xcelium, Indago, Coherency Concepts

Industry

Software Development

Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities : Design Verification for interconnect IP and Tensilica Processor subsystems. Relevant experience in interconnect and subsystems is strongly preferred Crafting verification plans and executing on those plans to verify highly complex and configurable designs. Responsible for coverage collection and closure Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope Responsible for creating / working with UVM based DV environment. Required Skills and Experience: 10+ years of design verification experience BS (or higher) in EE/Computer Engineering Strong technical and interpersonal skills Excellent knowledge of Interconnects, NoCs and design verification fundamentals. Excellent knowledge and command over AMBA protocols like AXI, AHB and APB. Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches Exposure to scripting languages like Perl, Unix shell or similar languages Understanding of Coherency concepts will be a plus Experience with Formal Verification will be a plus Experience with development of fully automated flows Experience with Gate Level Simulations Excellent written and oral communication skills necessary Experience with integrated verification flows for processors with C and SV language is a plus Good experience with Simulation and Debugging tools like Cadence Xcelium, Indago etc. We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Responsibilities

Responsible for design verification of interconnect IP and Tensilica Processor subsystems, including crafting and executing verification plans. The role involves coverage collection, closure, and developing UVM-based DV environments in collaboration with cross-functional teams.