Sr. Principal Engineer, IP Design (ASIC) at SK hynix memory solutions America Inc.

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

13 May, 26

Salary

0.0

Posted On

12 Feb, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC/SoC Design, RTL Design, Verilog/SystemVerilog, Design Verification, Timing Closure, Static Timing Analysis (STA), Logic Design, Synthesis, Clock Domain Crossing (CDC), Python/Tcl/Perl Scripting, Micro-architecture, IP Ownership, PPA Optimization, Linting, Mentorship, High-Speed Interfaces

Industry

Semiconductor Manufacturing

Description

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing. About the Role You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions. As a Senior Principal Engineer, you will own critical IP blocks end-to-end, drive methodology improvements (such as AI-assisted design flows), and mentor staff engineers to ensure first-pass silicon success. Responsibilities Lead End-to-End IP Ownership: Architect, design, and verify complex IP blocks or subsystems for high-performance memory controllers, taking ownership from specification to tapeout. RTL Design & Integration: Develop efficient, high-speed RTL (Verilog/SystemVerilog) for critical modules, ensuring optimization for power, performance, and area (PPA). Design Verification & Quality: Oversee design reviews, linting, Clock Domain Crossing (CDC) analysis, and power analysis to ensure robust functional and timing closure. Cross-Functional Leadership: Collaborate deeply with verification, DFT, physical design, and firmware teams to resolve complex system-level bottlenecks and ensure seamless integration. Methodology Innovation: Drive enhancements in design automation (Python/Tcl/Perl) and best practices for synthesis and static timing analysis (STA) to improve team efficiency. Mentorship: Mentor junior and staff engineers on advanced design techniques, code quality, and debugging strategies. Minimum Qualifications Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. Experience: 12+ years of hands-on experience in ASIC/SoC design with a proven track record of successful tapeouts. Technical Mastery: Expert proficiency in Verilog/SystemVerilog, logic design, synthesis, and STA for high-speed digital circuits. Tool Proficiency: Strong experience with industry-standard EDA tools (Synopsys/Cadence) for simulation, linting, and CDC analysis. Communication: Demonstrated ability to lead technical discussions and document complex micro-architectures clearly for cross-functional teams. Preferred Qualifications Advanced Education: Master’s or PhD in Electrical Engineering with 8+ years of applicable experience. Domain Knowledge: Deep understanding of memory controller architectures (PCIe/NVMe, DDR, NAND Flash) or error correction algorithms. High-Speed Design: Experience designing for high-frequency interfaces or data center/enterprise applications. Scripting/Automation: Proficiency in Python, Tcl, or Perl for design automation and flow optimization. Leadership: Previous experience serving as a technical lead or architect for a major subsystem or IP block. Key Projects: Enterprise SSD Controllers for AI/Data Centers: Designing best-in-class SoCs tailored for high-throughput, low-latency enterprise workloads, crucial for AI training and inference clusters. Hardware Accelerators for Reliability: Developing dedicated hardware accelerators and AI/ML-based error correction algorithms to automate operations and enhance data reliability without sacrificing power or latency. Next-Gen Interface Integration: Working on controllers that integrate the latest high-speed protocols (PCIe Gen6/7, UCIe, NVMe) to maximize data transfer rates for "Silicon Skyscraper" 3D-IC architectures. Why Join Us? Direct Impact on AI Infrastructure: You won't just be designing generic chips; you will be building the storage engines that power the global AI ecosystem. SK hynix is a key player in the AI memory landscape (HBM, eSSD), and your work directly addresses the "memory bottleneck" in high-performance computing. Stability Meets Agility: We offer the resources and stability of a global semiconductor giant (SK hynix Inc.) combined with the agile, innovation-driven culture of a San Jose R&D subsidiary. Comprehensive Benefits: 401(k) matching, onsite gym and cafeteria (breakfast/lunch/dinner), and generous health coverage, ensuring you are supported both professionally and personally. REGARDING COMPENSATION: SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth. The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness

Responsibilities

The engineer will lead the end-to-end ownership of critical IP blocks, including architecture, design, and verification for high-performance memory controllers, ensuring successful tapeout. Responsibilities also involve driving methodology improvements, such as AI-assisted design flows, and mentoring staff engineers.