Sr. Staff Engineer, Analog/Mixed-signal IC Layout at Ayar Labs

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

17 Sep, 26

Salary

160000.0

Posted On

19 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Analog IC Layout, Mixed-Signal IC Layout, FinFET Process Nodes, Cadence Custom Layout Tools, Calibre DRC/LVS, High-Speed SerDes, Floor Planning, Parasitics Analysis, Crosstalk Isolation, Python, SKILL, PLL Layout, RF Amplifiers, High Speed Transmitters/Receivers

Industry

Computer Hardware Manufacturing

Description

Sr. Staff Engineer, Analog/Mixed Signal IC Layout Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are seeking an exceptionally skilled and experienced Sr. Staff IC Layout Engineer, to join our Silicon Engineering team. In this senior role, you will be responsible for the physical implementation of complex, high-performance integrated circuits, with a primary focus on custom analog, mixed-signal, and/or high-speed digital blocks. The ideal candidate is a recognized expert in the latest advanced semiconductor process nodes, capable of driving layout methodologies and ensuring the physical design meets aggressive performance, power, and area targets Key Responsibilities: * Performing physical layout for critical mixed-signal components within high speed SerDes using Cadence tools. * Work with AMS design engineers to optimize layout for performance and reliability. * Take part in floor planning, custom layout and verification against design rules and schematics. * Define, develop, and implement advanced layout and verification methodologies for FinFET process technologies to maximize design efficiency. Establish and maintain layout standards, design rules, and best practices across the team. Required Qualifications: * Associates Degree, or equivalent experience * 10+ years of hands-on analog/mixed signal layout experience, with at least 5+ years in FinFET nodes * A good understanding of high-speed design/layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc. * Proficient with Cadence custom layout tools * Knowledge of DRC/LVS checking flows with Calibre Preferred Qualifications: * Experience with integration between custom AMS and digital components in the latest FinFET nodes. * Some knowledge of scripting languages such as Python and SKILL. * Previous experience laying out sensitive analog blocks such as PLLs, RF amplifiers, and high speed transmitters/receivers. * Excellent communication skills with the ability to clearly articulate complex technical issues and solutions to cross-functional teams. Salary Range: $140,000 - $160,000 NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers. Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

Responsibilities

Responsible for the physical implementation of complex, high-performance integrated circuits focusing on custom analog, mixed-signal, and high-speed digital blocks. This includes performing layout for SerDes components, optimizing for performance and reliability, and developing FinFET layout methodologies.