Start Date
Immediate
Expiry Date
02 Jul, 26
Salary
0.0
Posted On
03 Apr, 26
Experience
5 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
System Verilog, UVM, RTL simulation, Gate-level simulation, Functional coverage, Code coverage, Debugging, Computer architecture, Python, C, C++, Java, Object oriented programming, DDR protocol, Mixed signal verification
Industry
Semiconductor Manufacturing