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SSTC_AI Chip and Middleware Engineer Intern (A000) at ITRI
, , -
Full Time

Start Date

Immediate

Expiry Date

05 May, 26

Salary

0.0

Posted On

04 Feb, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

AI Accelerator Hardware Architecture, Performance Analysis, System-Level Modeling, RISC-V Computing Architecture, Instruction Set Extensions, FPGA Development, Integration, Verification, Deep Learning Models, AI Inference Principles, Processor Architecture Design, QEMU Development, Linux Kernel Development, Computer Organization, Microarchitecture Analysis, Image Processing Algorithms

Industry

Research Services

Description
This internship is in ITRI's Service Systems Technology Center(SSTC). We are looking for talents to join us in AI chip system design and instruction set extensions for applications such as Artificial Intelligence and High‑Performance Computing (HPC). Candidates with any of the following expertise are welcome: AI accelerator hardware architecture performance analysis and system‑level modeling/simulation RISC‑V computing architecture, instruction set extensions, and development of simulation platforms (e.g., QEMU) FPGA platform development, integration, and verification (including test data flow validation) Qualifications: Relevant majors include Computer Science, Electrical and Electronic Engineering, or related disciplines. Language proficiency: Intermediate English proficiency (listening/speaking/reading/writing). Professional Skills / Tools: Proficiency in at least one programming language: C, C++, or Python. Candidates with any of the following expertise will receive priority consideration: Deep learning models and AI inference principles Processor / AI accelerator / SoC architecture design QEMU or Linux kernel development Computer organization and microarchitecture analysis Familiarity with the following languages is a plus: Verilog, SystemC, C/C++, Python The following hands-on experience is highly preferred: Image processing algorithms Deep learning model architectures RISC-V FPGA development
Responsibilities
The intern will assist in AI chip system design and instruction set extensions for applications in AI and HPC. They will work on performance analysis and system-level modeling/simulation.