PREFERRED EXPERIENCE:

• Worked with EDA tools that enable RTL quality checks
• Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
• Ability to multitask, grasp new flows/tools/ideas.
• Experience in improving the methodologies.
• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.
• Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)
• Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters
• Strong analytical and problem-solving skills

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:

THE ROLE:

AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate’s responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC (timing constraints) development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred.

KEY RESPONSIBILITIES:

• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
• Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency.
• Implement the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks.
• collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows.
• Require a blend of SDC experise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)
• Continuously review and identify areas for process improvements and early issue detection during the design phase.