STA Engineer at Apple

Cupertino, California, United States -

Full Time

Start Date

Immediate

Expiry Date

16 Apr, 26

Salary

0.0

Posted On

16 Jan, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Design, ASIC Design, Timing Concepts, Scripting Languages, TCL, Python, Perl, STA Tools, Timing Constraints, Timing Corners, Synthesis, Logic Equivalence Checks, Self-Starter, Highly Motivated, Communication

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. DESCRIPTION As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis. MINIMUM QUALIFICATIONS Bachelors Degree + 0 Years of Experience. PREFERRED QUALIFICATIONS Strong fundamentals in the area of Digital design Familiarity with ASIC design timing concepts Proficient in scripting languages (TCL, Python and Perl) Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks Self-starter and highly motivated Ability to communicate optimally across all internal groups

Responsibilities

As an ASIC STA Engineer, you will be responsible for full chip and block level timing closure and constraints ownership throughout the project. You will collaborate with various SOC teams to execute design and integration tasks for high-quality IP deliverables.