Staff AI Engineer, Circuit Design (TFT & Pixel) at Samsung Semiconductor
San Jose, California, USA -
Full Time


Start Date

Immediate

Expiry Date

30 Nov, 25

Salary

243000.0

Posted On

31 Aug, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Good communication skills

Industry

Electrical/Electronic Manufacturing

Description

PLEASE NOTE:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

WHAT YOU BRING

  • BS Computer Science or equivalent with a minimum of 10+ years or a MS in Computer Science with 8+ years or PhD 5+ years in Electrical Engineering/Computer Engineering/Applied Physics (or equivalent experience).
  • Proficiency with SPICE/Spectre/HSPICE/Cadence Virtuoso/ADE; layout and parasitic extraction.
  • Strong Python and ML fundamentals (PyTorch or TensorFlow, scikit-learn/NumPy/Pandas)
  • Experience building and validating surrogate models and running multi-objective optimization.
  • Experience with GNNs for layout-to-electrical, PINNs/physics-informed ML, or differentiable simulation.
  • RL for control/param tuning; Bayesian optimization at scale; DoE/active learning.
  • Publications/patents in display, EDA, or ML-for-hardware.
  • Solid analog/digital circuit fundamentals; hands-on OLED pixel/gate driver design.
  • Demonstrated ability to take designs from simulation to hardware bring-up and correlation.
  • You’re inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.

    LI-VL1

How To Apply:

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Responsibilities

AI for design & optimization

  • Develop physics-informed ML and GNN surrogates mapping layout/process to electrical KPIs.
  • Run multi-objective optimization via Bayesian optimization/evolutionary search; generate candidate pixel, driver topologies.
  • Apply RL for process control and compensation strategy tuning.

Circuit Simulation

  • Compose fast design loops that combine Layout/SPICE with learned surrogates; accelerate what-if sweeps.
  • Build data/feature pipelines from fab/test and panel bring-up; implement active learning and uncertainty quantification.
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