Knowledge and experience in the following is a definite advantage:

• Implementation and delivery of GPU cores from RTL to GDSII

• Semi-custom design flow and methodology development

• Identifying areas for flow and process improvements

• Verilog and System-Verilog languages

• RTL synthesis using physically aware tools

• Design constraint management for power, timing, clocking, interfaces

• Formal Verification for RTL-netlist and netlist-netlist checks

• Clock Tree Analysis and Optimization

• ECO methods for functional and timing fixes

• Managing design goals and tradeoffs in power, performance, and area

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Preferred Qualifications

At-least 5-7 years of experience developing methodologies for PPA improvement

Basic understanding of digital design and RTL development

Hands on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower,PrimeTime and Prime Closure

Script writing experience in UNIX shell, Python, Perl and/or TCL

• Excellent interpersonal and analytical skills as well as ability to work independently