Staff Design Engineer, TSV Packaging at Micron Technology

Boise, Idaho, United States -

Full Time

Start Date

Immediate

Expiry Date

05 Jan, 26

Salary

0.0

Posted On

07 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Semiconductor Packaging, Thermal Compression Bonding, Finite Element Analysis, Simulation, Mechanical Design, Material Science, EDA Techniques, ANSYS, Abaqus, SolidWorks, MATLAB, Fracture Simulations, Product Reliability Tests, Data Acquisition, Numerical Analysis, Collaboration

Industry

Semiconductor Manufacturing

Description

Stay up-to-date on semiconductor and advanced electronics packaging technologies like High Bandwidth Memory (HBM) and Flip Chip. Detailed understanding of thermal compression bonding process for chip-on-wafer and wafer-to-wafer hybrid bonding process and the corresponding Multiphysics mechanisms involved to capture in the simulation. Collaborate daily with global teams in product design, engineering, technology, and business units to analyze manufacturing processes using simulation. Understanding of packaging materials and their production processes. Work with internal/external vendors and testing labs to craft and implement effective testing procedures to characterize materials for simulation analysis. Maintain an understanding of measurement methodologies and coordinate measurement data collection of packages and packaging materials for correlation of simulation activities. Develop semiconductor packages with advacned EDA techniques and simulation tools like ANSYS, Icepak, Flotherm. 8+ years working experience in Mechanical and Thermo-mechanical finite element analysis, modeling and validation of electronic packages in Semiconductor industry or equivalent. Engineering tools: ANSYS Workbench, APDL, Abaqus, ProE or equivalent experience, AutoCAD, Solid Works, MATLAB. M.S. / Ph.D. in Mechanical Engineering, Material science, or related Engineering field. Simulation, modeling, and analysis of thermos-mechanical problems by multi-physics with software like Ansys, COMSOL, etc. Proven academic training and research experience in Solid and fluid mechanics. Experience in performing fracture simulations for IC packages. Experience in semiconductor process simulation like wafer-to-wafer bonding process, thermal compression bonding process, mass reflow process, die ejection process, etc. Ability to bring to bear the distributed team members and develop new characterization methods for new designs. Knowledge in product reliability tests like thermal cycling, and other environmental stresses. Mechanical design capability (2D, 3D) with SolidWorks, AutoCAD, etc. Good documentation/reporting skills and the ability to build and improve simulation and procedures for accurate and repeatable results. Data acquisition experience and numerical analysis proficiency in MATLAB, Excel, JMP, etc. Seeking a dedicated, motivated individual to balance tasks efficiently, work well in a team.

Responsibilities

The Staff Design Engineer will stay updated on semiconductor packaging technologies and collaborate with global teams to analyze manufacturing processes using simulation. They will also develop semiconductor packages and implement effective testing procedures for material characterization.