STAFF ENG-HIG-HBM-LAYOUT at Micron Technology

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

08 Apr, 26

Salary

0.0

Posted On

08 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

IC Layout Design, LVS Verification, DRC Verification, Analog Design, Mixed-Signal Design, Digital Design, Project Management, Collaboration, Mentorship, Quality Assurance, Time Estimation, Scheduling, Communication, Problem Solving, Tapeout Experience, Memory Layout Principles

Industry

Semiconductor Manufacturing

Description

Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Lead the layout design and development of complex analog, mixed-signal, and digital blocks and full chip level integration Ensure timely delivery of high-quality block-level layouts, meeting project milestones and design specifications. Perform layout verification including LVS, DRC, and antenna checks, along with thorough quality reviews and documentation. Collaborate with global engineering teams to ensure successful execution and integration of layout projects. Provide technical guidance and mentorship to junior team members, reviewing sub-block layouts and supporting their development. Demonstrate leadership in planning, time estimation, scheduling, and execution across multiple projects. Contribute actively to project management and cross-functional coordination. Proven experience in IC layout design with a systematic and methodical approach. Strong attention to detail and a passion for high-quality design. Excellent communication and collaboration skills, especially in a global team environment. Ability to manage multiple priorities and deliver results under tight timelines. Experience: 8-15 years in Memory /Analog/Custom layout design across advanced CMOS process nodes, including Planar and FinFET technologies. Tool Proficiency: Strong expertise in Cadence VLE/VXL and Mentor Graphics Calibre for DRC/LVS verification is essential. Technical Expertise: Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. Fundamentals: Solid understanding of Memory /Analog layout principles including bit cell , addressing , banking ,matching, electromigration, latch-up, coupling, crosstalk, IR-drop, and parasitic effects. Design Awareness: Ability to assess and mitigate layout impacts on circuit performance—speed, capacitance, power, and area. Memory Architecture: Familiarity with design hierarchies and memory layout architectures is a plus. Verification Skills: Strong problem-solving skills in physical verification and debugging of custom layouts. Tapeout Experience: Prior involvement in multiple successful tapeouts is highly desirable. Project Management: Proven ability to manage multiple layout projects, ensuring quality and timely delivery at all stages. Communication: Excellent verbal and written communication skills, with the ability to collaborate effectively across global teams. BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Responsibilities

Lead the layout design and development of complex analog, mixed-signal, and digital blocks while ensuring timely delivery of high-quality layouts. Collaborate with global engineering teams and provide technical guidance to junior team members.