Staff Engineer, ASIC Development Engineering (FPGA-RTL Design) at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

08 Apr, 26

Salary

0.0

Posted On

08 Jan, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

FPGA Design, RTL Logic Design, SystemVerilog, UVM, Digital Designs, Synthesis, STA, Optimization Flows, Vivado, Synplify, NCSim, VCS, Python, Perl, AI/ML Techniques, Board-Level Design

Industry

Semiconductor Manufacturing

Description

Company Description At Sandisk, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, Sandisk is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon. We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future. Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too. We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands. Today’s exceptional challenges require your unique skills. It’s You & Sandisk. Together, we’re the next BIG thing in data. Job Description The FPGA design team, part of the (VHS) group is responsible for developing a wide range of FPGA solutions for post-silicon validation of memory devices across Western Digital. Your main responsibilities as part of a winning group: Complex logic blocks & IPs design Work in a multi-disciplinary environment with a variety of complex interfaces. Qualifications B.Tech/M.Tech in Electrical Engineering, Computer Engineering, or equivalent. Experience 5 to 7 years of hands-on experience in RTL logic design. Strong SystemVerilog expertise; SV/UVM-based simulation knowledge is a plus. Experience in multi-clock, high-frequency, and high-performance digital designs. Familiarity with synthesis, STA, and optimization flows. FPGA development experience (Vivado / Synplify) is an advantage. Simulation and verification experience using NCSim, VCS, or equivalent tools. Knowledge of standard storage interfaces such as eMMC or UFS is a strong advantage. Scripting experience with Python/Perl for automation; ML-driven automation experience is a plus. Exposure to board-level design or lab bring-up is an added advantage. AI/ML-Relevant Additions Experience applying AI/ML techniques for RTL linting, verification acceleration, or design-space exploration is a strong plus. Familiarity with ML-based test generation, pattern prediction, or EDA tool automation preferred. Ability to integrate ML-assisted workflows (e.g., regression triage, anomaly detection, coverage prediction). Soft Skills Strong communication skills across cross-functional and global teams. Ability to collaborate across multiple interfaces and domains. Innovative mindset and proactive approach to problem-solving. Effective team player with ownership and accountability. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore Cosmos Office--LOC_WDT_Bangalore Cosmos Office

Responsibilities

The FPGA design team is responsible for developing a wide range of FPGA solutions for post-silicon validation of memory devices. Key responsibilities include designing complex logic blocks and IPs while working in a multi-disciplinary environment.