Staff Engineer, ASIC Development Engineering (IP Verification ) at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

11 Mar, 26

Salary

0.0

Posted On

11 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Verification, SystemVerilog, SVA, UVM, EDA Tools, FPGA, Testbenches, Debugging, Standard Protocols, Perl, Python, AI/ML, Problem-Solving, Communication, Collaboration, Version Control

Industry

Semiconductor Manufacturing

Description

Company Description At Sandisk, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, Sandisk is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon. We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future. Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too. We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands. Today’s exceptional challenges require your unique skills. It’s You & Sandisk. Together, we’re the next BIG thing in data. Job Description The FPGA design team, part of the (VHS) group is responsible for developing a wide range of FPGA solutions for post-silicon validation of memory devices across Western Digital. Your main responsibilities as part of a winning group: Complex logic blocks & IPs design Work in a multi-disciplinary environment with a variety of complex interfaces. Qualifications BE/ME in ECE, Electronics, or a related engineering discipline. 5–7 years of hands-on experience in RTL verification at Block/IP/Sub-system/SoC levels. Proficient in SystemVerilog for verification; advanced experience with SVA and UVM is a strong advantage. Deep knowledge of EDA tools such as Cadence NCSim, SimVision, vManager, and waveform-debug tools from Mentor/Synopsys. Experience with FPGA-based verification environments. Practical experience with SV- UVM-based simulation environments. Skilled in developing testbenches for constrained-random and metric-driven verification. Strong debugging capability with the ability to root-cause design issues and communicate findings clearly in written form. Exposure to standard protocols such as eMMC, UFS, USB, PCIe, and DDR4 is an advantage. Proficiency in Perl/Python scripting; ability to automate flows, logs, and regressions. Understanding of AI/ML fundamentals as applied to hardware verification workflows. Experience using ML techniques for regression triage, failure clustering, anomaly detection, or coverage prediction. Strong problem-solving skills with the ability to break down complex issues and apply appropriate techniques to achieve results. Excellent communication and collaboration skills across local and global teams. Ability to coordinate and communicate across multiple interfaces within the organization. Innovative mindset; capable of leveraging new technologies, including AI/ML, to improve verification efficiency, organizational workflows, and alignment between technical and business goals. Familiarity with version control systems such as Git.

Responsibilities

The main responsibilities include designing complex logic blocks and IPs, and working in a multi-disciplinary environment with various complex interfaces. The role is part of the FPGA design team responsible for developing FPGA solutions for post-silicon validation of memory devices.