Staff Engineer, ASIC Development Engineering at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

30 Sep, 26

Salary

0.0

Posted On

02 Jul, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Serdes PHY Layout, Analog Mixed-Signal IC Layout, Block PnR, Cadence, Synopsys, Mentor Graphics, FinFET Technology, Signal Integrity, ESD Mitigation, EMIR Debugging, LVS/DRC/ERC, Custom Digital Layout

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are seeking a highly skilled High-speed SERDES IO PHY Layout designer with 5 - 9 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, Automated PnR and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work experience of block PnR to closely interact with physical design team ensuring area/timing/backend compatibility of custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct layout reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field. 5-10 years of experience in IO/Analog mixed-signal IC layout design and block level PnR Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs, and ESD circuits. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 7nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL, Python and SVRF) for automation tasks. Additional Information Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the Equal Employment Opportunity is the Law poster. Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

Develop and optimize high-speed Serdes PHY and analog mixed-signal IC layouts to ensure high performance and manufacturability. Collaborate with design engineers to resolve layout-related issues and ensure backend compatibility of custom blocks within the overall chip design.