Staff Engineer - Chip Lead at Silicon Labs

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

31 Jan, 26

Salary

0.0

Posted On

02 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SoC Development, Architecture, Micro-Architecture, Digital Design, High-Speed Interfaces, Peripheral Interfaces, RISC-V, ARM, Design Signoff, Low Power Design, Hardware Accelerators, Verilog, System Verilog, Scripting Languages, Project Management, Team Leadership

Industry

Semiconductor Manufacturing

Description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. The Role: This position involves the development of complex SoC/chip architectures with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture and multi-level caches, multiple clocks and resets, high-speed interfaces, peripherals. The chosen candidate would need to contribute to, and manage a team for, the development of architecture, microarchitecture, and design of SoCs which include RISC-V, ARM or proprietary processor designs, and high-speed interfaces for off-chip memories, along with the integration of wireless systems, power management, and mixed signal IP. The candidate would be responsible for the leading a project through the entire product development process. Responsibilities Lead the development and execution of Wireless SoC’s from definition, through execution, and into production Definition and Planning Coordinate with the product marketing teams to develop the SoC requirements. Provide the necessary design collateral to support the product approval gates. Develop and maintain the SoC architecture or technical specification to meet the product requirements, with a key goal to maximize IP reuse. Develop the design schedule, including milestones and resource requirements. Coordinate with cross functional teams (such as software) on dependencies. Project Execution Coordinate with global design functional leads (RF, baseband, verification, etc) to track execution, triage issues, and perform prudent escalation. Represent the design community to provide succinct weekly status and attend the cross functional meeting. Drive design action items to closure. Perform SoC Design Integration and maintain design collateral such as documentation, register libraries, and pinouts delivered to cross functional teams. Follow established quality procedures and processes to achieve first tapeout. Validation to Production Actively support the validation and product test teams during silicon bringup, validation, characterization, and qualification. Triage, track, and resolve issues reported during silicon evaluation. Execute a metal or full layer revision, if necessary Minimum Qualifications: Bachelor or Master’s degree in Electrical or Computer Engineering, 10+ years in Industry Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus. Top-down planning and execution of SOC projects. Experience in full-chip development cycle Able to build strong technical team. Hands-on experience in architecture, micro-architecture, digital design processes Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN, etc. Knowledge of processors like RISC-V and ARM processors Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure Knowledge of DFT including Scan, ATPG, MBIST Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling) Knowledge of hardware accelerators Knowledge of Verilog and System Verilog Knowledge of scripting languages like Perl, Python, Tcl, shell Benefits & Perks: Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun. Equity Rewards (RSUs) Employee Stock Purchase Plan (ESPP) Insurance plans with Outpatient cover National Pension Scheme (NPS) Flexible work policy Childcare support Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law. At Silicon Labs, we hire and empower great talent to achieve their full potential. By offering challenging projects, technical mentorship, and continuous learning opportunities, we ensure our employees thrive at every stage of their careers. Here, you’ll work alongside some of the industry’s brightest minds, tackling complex problems that deepen your expertise and expand your horizons. Whether you’re building new skills or shaping your career path, we’re dedicated to supporting your growth and celebrating your success every step of the way. Please note that our Company never asks for personal information unrelated to the job application process, such as bank or credit card data and never charges any fees to apply to any jobs. For more information please click here.

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Responsibilities

Lead the development and execution of Wireless SoCs from definition through execution and into production. Coordinate with cross-functional teams to ensure project milestones are met and issues are resolved.