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STAFF Engineer- DEG Layout at Micron Technology

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

07 Jan, 26

Salary

0.0

Posted On

09 Oct, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Layout Quality Guidelines, Silicon-Proven Tape-Outs, Place and Route Tech Files, Calibre DRC, Power Planning, IR Drop Analysis, EM Analysis, Logic Block Verification, Chip-Level Verification, Standard Cell Layouts, Routing Challenges, PPA Specifications

Industry

Semiconductor Manufacturing

Description

Responsibilities will include, but are not limited to: Ensure all the layout done and released from India team is as per quality guidelines, show continuous improvement in the quality of layout. Responsible for release of block on time as per the quality guidelines. Working experience in multiple silicon-proven tape-outs with multimillion gate count designs. Experience in writing and modifying place and route tech files and calibrating with Calibre DRC. Experience in power planning, IR drop, and EM analysis. Experience in logic block and chip-level verification. Ability to understand standard cell layouts and guide the team based on routing challenges to meet target PPA specifications.

Responsibilities

Ensure all layouts released from the India team meet quality guidelines and show continuous improvement. Responsible for timely release of blocks while adhering to quality standards.