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Staff Engineer Design Verification at Infineon Technologies AG Australia
Bengaluru, karnataka, India -
Full Time

Start Date

Immediate

Expiry Date

12 Feb, 26

Salary

0.0

Posted On

14 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Verification, IPs, SoCs, ASIC Verification, Verilog, System Verilog, UVM, Test Benches, Power Aware Verification, Gate Level Verification, Ethernet, MIPI Protocols, Display Port

Industry

Semiconductor Manufacturing

Description
Experience and knowledge in Verification ofIPs/SoCs related to different applications. B.E./B.Tech/M.E./M.Tech in ECE or equivalent Bachelor's - 6 to 7 years of experience/ Master's - 5 to 6 years of experience Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Should be able to develop IP/SoC test benches. Experience and knowledge in Verification ofIPs/SoCs related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Knowledge on Ethernet (IEEE 802.3), MIPI protocols, Display Port is preferable. We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Leading sub tasks in IP/SoC Verification. Contributes significantly for the Verification of complex IPs/SoCs Verification Requirements creation at IP/SoC level as per the design requirements and UVM Test benches creation Support in building verification infrastructure at the IP/Chip level as per the requirements Support in different areas of SoC Verification: RTL, Power Aware and Gate Level Verification

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Responsibilities
Lead sub-tasks in IP/SoC Verification and contribute significantly to the verification of complex IPs/SoCs. Support in building verification infrastructure at the IP/Chip level and in different areas of SoC Verification.