About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Digital IC Design Staff Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.
This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.
What You Can Expect
Design and Verification of DFT logic and components. Generate structural test vectors, analysis, and coverage improvement. Work on understanding DFT techniques for various communication and automotive chips. Generate timing constraints for all DFT modes. Work with implementation teams on DFT STA, logical, physical, and power issues. Develop test methodologies for ATPG at block and system level. Perform scan insertion in various commercial chips. Support ATE team with test vector porting, diagnosis, and physical failure analysis.
What We’re Looking For
Master’s or foreign equivalent degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

Must have work/internship experience or completed graduate coursework/research in each of the following:

• SoC development with ASIC DFT design.
• DFT circuit insertion and validation for scan, at-speed, MBIST and Boundary scan.
• Industry standard DFT/ATPG EDA tools like Tessent, TestMax, Modus.
• Simulators and waveform debug tools.
• DFT methodologies, industrial standards, and practices.
• Chip design, Verilog/System Verilog, and design verification.
• STA tools like Primetime, SDF generation and RTL and Gate-level simulations of UVM, SystemVerilog.
• Verilog HDL based Netlists, design libraries and Scripting (Perl/Tel).

Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our
Careers
page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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Please refer the Job description for details