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Staff Engineer Functional Digital Verification (f/m/div) at Infineon Technologies AG Australia

Villach, Carinthia, Austria -

Full Time

Start Date

Immediate

Expiry Date

12 Feb, 26

Salary

0.0

Posted On

14 Nov, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Verification, Mixed Signal Designs, Verification Plans, SystemVerilog, Universal Verification Methodology, Constrained Random Approach, RTL Design, Gate-Level Testing, Debugging, Analog and Digital Design, Mentoring, Cadence Verification Software, Xcelium, vManager, GIT, Python

Industry

Semiconductor Manufacturing

Description

Create and define verification plans, for digital verification of Mixed Signal designs Create new and improve existing verification environments in SystemVerilog language using Universal Verification Methodology (UVM) and Constrained Random approach Execute tests in these environments on RTL and gate-level and debug issues in design and verification environments Closely cooperate with analog and digital designers as well as concept and other verification engineers Mentoring of junior colleagues, consultants, and students You work conscientiously on making things better, faster, and more efficient and keep up high quality standards for yourself and other people. You can solve technical problems and work independently. You are a team player and support your colleagues for the overall team and company success. A university degree in Electrical Engineering, Computer Science, Information Technology, or a similar academic discipline Ideally 3-5 years of related work experience Excellent know-how with UVM, especially using System Verilog knowledge of RTL design (HDL) and digital or analog circuits knowledge of Cadence verification software (Xcelium and vManager) or similar knowledge of GIT, Python, and other programming languages as a plus Fluency in English We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.

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Responsibilities

Create and define verification plans for digital verification of Mixed Signal designs. Execute tests in these environments on RTL and gate-level and debug issues in design and verification environments.