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Staff Engineer at Infineon Technologies AG Australia
Ahmedabad, gujarat, India -
Full Time

Start Date

Immediate

Expiry Date

27 Feb, 26

Salary

0.0

Posted On

29 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Digital Designs, Synthesis, STA, Timing Constraints, Power Analysis, DFT Flows, Logic Equivalence Check, UPF Concepts, Low Power Checks, PVT Corners, OCV, AOCV, POCV Derates, Prime-Time, TEMPUS, Signal SI Analysis

Industry

Semiconductor Manufacturing

Description
Implement high-performance, low-power, and area-efficient digital designs. Strong fundamentals and experience in Synthesis and STA domains. Write and implement block level and top-level timing constraints for Synthesis Optimize designs for power, performance, and area, and meet design goals. Knowledge on Power analysis and PT-PX flow. Understanding of DFT flows, including scan insertion. Write and evaluate Test/DFT mode timing constraints. Thorough with Logic Equivalence Check debug capability. Well known about UPF concepts and Low Power Checks at block and full chip level. Defining and verification of STA constraint for Functional and Test/SCAN Modes. Defining PVT's corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.

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Responsibilities
Implement high-performance, low-power, and area-efficient digital designs. Optimize designs for power, performance, and area while meeting design goals.